IBM researchers working on next-generation chip-cooling technologies

A team of IBM researchers collaborating with two Swiss university partners aims to extend Moore’s Law another 15 years by using 3-D stack architectures with liquid cooling microchannels. This law states that the number of transistors that can be placed inexpensively on an integrated circuit doubles every 18 months. It has held true for more than 50 years, but extending it to 2020 will require a change from simple transistor scaling to novel packaging architectures such as the vertical integration of chips (3D integration).

IBM, École Polytechnique Fédérale de Lausanne (EPFL) and the Swiss Federal Institute of Technology Zurich (ETH) have launched a joint four-year project called CMOSAIC, which will investigate how the latest chip cooling techniques can support 3D chip architectures. The project will examine a 3D multi-core stack architecture with a interconnect density ranging from 100 to 10,000 connections per square millimetre.

The research aims to do more than just extend Moore’s Law. According to John R. Thome, professor of heat and mass transfer at EPFL and CMOSAIC project coordinator, data centres in the US already use two per cent of the available electricity, with consumption doubling every five years. In theory, at this rate a supercomputer in the year 2050 would consume the entire production of the US energy grid. 3D chip stacks with interlayer cooling not only yield higher-performance, but more importantly, enable much higher system efficiency, thereby avoiding the situation where supercomputers consume too much energy to be affordable.

If a large system on a chip (SoC) in is integrated in several layers, the average distance between the system components is reduced, which improves both efficiency and performance. However, removing the dissipated heat become increasingly difficult as chip dimensions become smaller, which makes cooling a key issue. The researchers expect that the combination of tiny interconnects and hair-thin liquid cooling microchannels only 50 microns in diameter between the active chips will be the key elements for achieving high-performance computing with future 3D chip stacks.

Source 1 : IBM press release

Source 2 :ETH project page

About pasanlaksiri

I am K.G. Pasan Laksiri Karunanayake and founder of Since 2011 I have specialized in designing custom electronics for industrial applications. Over the years I have engineered a broad range of custom industrial products. When I work with a client I place a very high value on integrity, honesty and clear communication. With years of field experience I have learned that all business relationships are personal relationships. The more I know about the client and his project, the more I can contribute to a successful end product. After I learn about the client requirement I always give them the better understanding and clear picture about, how the end product will function in real world. In addition to the client requirement, I also offer lots of options, features and improvements. And I always very concern about the end product quality.
This entry was posted in New Technologies and tagged , , , , . Bookmark the permalink.

1 Response to IBM researchers working on next-generation chip-cooling technologies

Leave a Reply

Fill in your details below or click an icon to log in: Logo

You are commenting using your account. Log Out /  Change )

Google photo

You are commenting using your Google account. Log Out /  Change )

Twitter picture

You are commenting using your Twitter account. Log Out /  Change )

Facebook photo

You are commenting using your Facebook account. Log Out /  Change )

Connecting to %s